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Lead Verification Engineer

Lead Verification Engineer | Edinburgh x2 a week | £65K + amazing benefits

Join our team in Edinburgh, Scotland, as a Digital Lead Verification Engineer within our experienced Controller IP Team. We are at the forefront of developing cutting-edge Intellectual Property (IP) for high-tech markets, enabling our customers to excel in IP-to-SoC development.

Key Responsibilities:

  • Architect Verification Environments for complex IP, including Ethernet, CXL, and Storage.
  • Develop UVM-SV Scoreboards for self-checking regressions.
  • Create Functional Coverage within Metric Driven Verification Environments.
  • Implement SystemVerilog Assertions for use in Formal and Simulation Environments.
  • Define and Manage Verification Plans (vPlans) using Cadence vManager tools.
  • Establish and Manage Automated Regression Environments, e.g., Jenkins.
  • Actively participate in Technical Review Meetings and Checklist Reviews in compliance with ISO-9001.
  • Collaborate closely with Design Engineers to debug complex test scenarios.


  • 4+ years of experience in microelectronics/EDA industry.
  • Essential experience in Verilog RTL Design.
  • Essential experience in Metric Driven Verification (MDV).

Please apply below, even if you do not meet all the criteria :)